1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing thereof. The invention particularly relates to a semiconductor device including capacitors with respective storage nodes adjacent to each other that are electrically isolated properly, and to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
As miniaturization of semiconductor devices advances, there arises a necessity of securing a sufficient capacitor area of a memory cell of a Dynamic Random Access Memory (hereinafter referred to as "DRAM") in order to obtain a prescribed capacitance. Various structures are proposed including three dimensional structures such as the pin structure and the crown structure as capacitor structures. Another structure is also proposed that is formed by roughening the surface of a capacitor electrode (storage node) to increase the surface area of the capacitor. Here, to roughen (roughening) refers to a process of generating hemispherical grains by growing crystal grains. The storage node having such a roughened surface is formed of a polysilicon film, and particularly referred to as HSG (Hemi Spherical Grained) polysilicon film or rough polysilicon film. Such a structure is hereinafter referred to as HSG polysilicon film. The HSG polysilicon film is obtained by forming an amorphous silicon film and annealing the amorphous silicon film in a disilane (Si.sub.2 H.sub.6) ambient.
Even if the HSG polysilicon film is applied to a storage node of a capacitor having a relatively simple structure, a sufficient surface area for the capacitor cannot be secured. Therefore, the HSG polysilicon film is applied to a storage node of a capacitor having the cylinder structure or the stacked trench structure for a DRAM which needs higher integration.
A conventional DRAM having a capacitor of the stacked trench structure is hereinafter described based on U.S. Pat. No. 5,760,434. A method of fabricating the DRAM, especially the memory cell portion is described by referring to the drawings attached. Referring to FIG. 19, one MOS transistor including a pair of sources drain regions 104a and 104b, and a gate electrode portion 106 is formed at a main surface of a semiconductor substrate 102 according to the known method. A silicon oxide film 108 is formed to cover gate electrode portion 106. A contact hole that exposes the surface of source.multidot.drain region 104b is formed at silicon oxide film 108, and a plug 109 is formed in the contact hole. An interlayer insulating film 110 is further formed on silicon oxide film 108. Prescribed photolithography and processing are applied to interlayer insulating film 110 to generate an opening 112 that exposes the surface of plug 109.
Referring next to FIG. 20, an amorphous silicon film 114 is formed on interlayer insulating film 110 to cover an upper surface of the interlayer insulating film 110, and a side surface and a bottom surface of opening 112 by, for example, CVD (Chemical Vapor Deposition). Referring to FIG. 21, amorphous silicon film 114 is annealed with a prescribed degree of vacuum and at a prescribed temperature to grow crystal grains at the surface of amorphous silicon film 114, and thus an HSG polysilicon film 114a having a roughened surface (hemispherical grains) is formed.
Referring to FIG. 22, HSG polysilicon film 114a formed on the upper surface of interlayer insulating film 110 is removed by, for example, etching. Accordingly, a storage node 116 having a roughened surface (hemispherical grains) in opening 112 is formed.
Referring to FIG. 23, a capacitor dielectric film 118 including a silicon oxide film and a silicon nitride film, for example, is formed on storage node 116. A cell plate 120 formed of a polysilicon film is placed on capacitor dielectric film 118. Storage node 116, capacitor dielectric film 118 and cell plate 120 constitute a capacitor. A main portion of a memory cell of a DRAM having one MOS transistor and one capacitor is thus completed. In the actual manufacturing process, an interlayer insulating film (not shown) is further formed to cover the capacitor, metal interconnection lines (not shown) and the like are formed on the interlayer insulating film, and accordingly, the DRAM is completed.
Problems with the method of manufacturing a DRAM described above are discussed below. The HSG polysilicon film formed on the upper surface of interlayer insulating film 110 is removed in the process illustrated in FIG. 22 in order to fabricate storage node 116 of the capacitor. In this process, if the HSG polysilicon film is removed by etching, silicon film residue 122 could be generated as shown in FIG. 24 by a non-uniform etching due to the hemispherical grains of the HSG polysilicon film, a native oxide film formed at the roughened surface, or the like. As a result, adjacent storage nodes 116 and 116 of the capacitors could be electrically short-circuited.
Even if the silicon residue does not cause the electric short-circuiting of adjacent storage nodes 116 and 116, a protruded portion 124 could be formed at cell plate 120 due to an abnormal growth of the polysilicon film of cell plate 120 located on silicon film residue 122, when cell plate 120 is formed on storage node 116. If an insulating film (not shown) deposited on cell plate 120 have a relatively small thickness, protruded portion 124 is not embedded in the insulating film to be electrically short-circuited with any metal interconnection line (not shown) formed on the insulating film.